Towards Multidimensional Verification: Where Functional Meets Non-Functional

Trends in advanced electronic systems' design have a notable impact on design verification technologies. The recent paradigms of Internet-of-Things (IoT) and Cyber-Physical Systems (CPS) assume devices immersed in physical environments, significantly constrained in resources and expected to provide levels of security, privacy, reliability, performance and low power features. In recent years, numerous extra-functional aspects of electronic systems were brought to the front and imply verification of hardware design models in multidimensional space along with the functional concerns of the target system. However, different from the software domain such a holistic approach remains underdeveloped. The contributions of this paper are a taxonomy for multidimensional hardware verification aspects, a state-of-the-art survey of related research works and trends towards the multidimensional verification concept. The concept is motivated by an example for the functional and power verification dimensions.Comment: 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC

Understanding multidimensional verification: Where functional meets non-functional

Abstract Advancements in electronic systems' design have a notable impact on design verification technologies. The recent paradigms of Internet-of-Things (IoT) and Cyber-Physical Systems (CPS) assume devices immersed in physical environments, significantly constrained in resources and expected to provide levels of security, privacy, reliability, performance and low-power features. In recent years, numerous extra-functional aspects of electronic systems were brought to the front and imply verification of hardware design models in multidimensional space along with the functional concerns of the target system. However, different from the software domain such a holistic approach remains underdeveloped. The contributions of this paper are a taxonomy for multidimensional hardware verification aspects, a state-of-the-art survey of related research works and trends enabling the multidimensional verification concept. Further, an initial approach to perform multidimensional verification based on machine learning techniques is evaluated. The importance and challenge of performing multidimensional verification is illustrated by an example case study

Reusing RTL assertion checkers for verification of SystemC TLM models

The recent trend towards system-level design gives rise to new challenges for reusing existing RTL intellectual properties (IPs) and their verification environment in TLM. While techniques and tools to abstract RTL IPs into TLM models have begun to appear, the problem of reusing, at TLM, a verification environment originally developed for an RTL IP is still under-explored, particularly when ABV is adopted. Some frameworks have been proposed to deal with ABV at TLM, but they assume a top-down design and verification flow, where assertions are defined ex-novo at TLM level. In contrast, the reuse of existing assertions in an RTL-to-TLM bottom-up design flow has not been analyzed yet, except by using transactors to create a mixed simulation between the TLM design and the RTL checkers corresponding to the assertions. However, the use of transactors may lead to longer verification time due to the need of developing and verifying the transactors themselves. Moreover, the simulation time is negatively affected by the presence of transactors, which slow down the simulation at the speed of the slowest parts (i.e., RTL checkers). This article proposes an alternative methodology that does not require transactors for reusing assertions, originally defined for a given RTL IP, in order to verify the corresponding TLM model. Experimental results have been conducted on benchmarks with different characteristics and complexity to show the applicability and the efficacy of the proposed methodology

On the Reuse of RTL assertions in Systemc TLM Verification

Reuse of existing and already verified intellectual property (IP) models is a key strategy to cope with the com- plexity of designing modern system-on-chips (SoC)s under ever stringent time-to-market requirements. In particular, the recent trend towards system-level design and transaction level modeling (TLM) gives rise to new challenges for reusing existing RTL IPs and their verification environment in TLM-based design flows. While techniques and tools to abstract RTL IPs into TLM models have begun to appear, the problem of reusing, at TLM, a verification environment originally developed for an RTL IP is still underexplored, particularly when assertion-based verification (ABV) is adopted. Some techniques and frameworks have been proposed to deal with ABV at TLM, but they assume a top-down design and verification flow, where assertions are defined ex-novo at TLM level. In contrast, the reuse of existing assertions in an RTL-to-TLM bottom-up design flow has not been analyzed yet. This paper proposes a methodology to reuse assertions originally defined for a given RTL IP, to verify the corresponding TLM model. Experimental results have been conducted on benchmarks of different characteristics and complexity to show the applicability and the efficacy of the proposed methodology

Design Understanding: From Logic to Specification

We present an outline of the field of Design Understanding and summarize state-of-the-art research in deriving human-understandable knowledge in form of logic properties from an unknown design

Improving ABV by generation and abstraction of PSL assertions

Lo scopo di questa tesi \ue8 quello di fornire le metodologie efficienti per migliorare ABV in tre settori della generazione, astrazione e qualificazione delle asserzioni PSL. I principali contributi di questa tesi possono essere riassunti come segue: 1- una metodologia di estrazione automatica \ue8 stato proposta, per catturare le descrizioni del comportamento di un sistema in grado di generare un insiemi di asserzioni temporali da tracce di esecuzione. L'approccio \ue8 particolarmente adatto per asserzioni minerarie che descrive le relazioni aritmetiche tra ingressi e uscite secondo un insieme di pattern temporali. In comparazione con lo stato dell'arte, l'affermazione minatore proposto in questa metodologia, genera una serie di affermazioni di qualit\ue0 pi\uf9 compatti e pi\uf9 alti. 2- una metodologia automatica astrazione che riutilizzare asserzioni originariamente definite per un dato IP RTL, per verificare il modello TLM corrispondente. La metodologia pu\uf2 essere diviso in due fasi principali, innanzitutto, asserzioni sintetizzate in metodi C ++ e in secondo luogo, inseriti nel modello TLM. I risultati mostrano che la metodologia pu\uf2 astrarre e riutilizzare le asserzioni da RTL a TLM ed evitare ridefinizione delle affermazioni che sono gi\ue0 esistenti a RTL. 3- una metodologia automatica qualificazione \ue8 stata proposta per valutare la qualit\ue0 di asserzioni e per misurare la interestingness di asserzioni. L'approccio ri-adatta metriche da data mining per misurare la qualit\ue0 delle asserzioni in base alla sua frequenza di attivazione durante simulazioni e la correlazione tra antecedente e conseguente. risultato sperimentale descrive la metodologia proposta fornisce una migliore stima di asserzioni interestingness.The aim of this thesis is to provide efficient methodologies to improve ABV in three domains of generation, abstraction and qualification of PSL assertions. The main contributions of this thesis can be summarized as follows: 1- An automatic mining methodology has been proposed, for capturing behavioral descriptions of a system that can generate set of temporal assertions from execution traces. The approach is particularly suited for mining assertions that describes arithmetic relations between inputs and outputs according to a set of temporal patterns. In comparation with state of the art, assertion miner proposed in this methodology, generates a set of more compact and higher quality assertions. 2- An automatic abstraction methodology has been proposed to reuse assertions originally defined for a given RTL IP, to verify the corresponding TLM model. The methodology can be divided into two main phases, firstly, assertions synthesized into C++ methods and secondly, inserted in the TLM model. The results show that the methodology can abstract and reuse assertions from RTL to TLM and avoid redefinition of assertions which are already exist at RTL. 3- An automatic qualification methodology has been proposed to evaluate the quality of assertions to measure the interestingness of assertions. The approach re-adapts metrics from data mining to measure the quality of assertions based on its activation frequency during simulation runs and the correlation between antecedent and consequent. Experimental result depicts the proposed methodology provides a better estimation of assertions interestingness

On the estimation of assertion interestingness

The definition of assertions is a fundamental phase for formal and semi-formal verification strategies as well as for documenting purposes. Assertions are generally manually defined, but several (semi-) automatic approaches have been also proposed that mine assertions directly from execution traces of the design under verification (DUV). In both cases, assertion qualification is necessary to evaluate the quality of the defined assertions. Current approaches evaluate the interestingness of a set of assertions by measuring the percentage of DUV\u2019s be- haviours covered by the assertions, mainly by adopting techniques based on mutation analysis, which require long simulation time. On the contrary, this work proposes an automatic technique to estimate the interestingness of assertions by ranking them according to metrics typically adopted in the context of data mining, which reveals to be a faster approach. Experimental results that compare the proposed assertion ranking strategy with assertion qualification based on mutation analysis are reported

Automatic extraction of assertions from execution traces of behavioural models

Several approaches exist for specification mining of hardware designs. Most of them work at RTL and they extract assertions in the form of temporal relations between Boolean variables. Other approaches work at system level (e.g., TLM) to mine assertions that specify the behaviour of the communication protocol. However, these techniques do not generate assertions addressing the design functionality. Thus, there is a lack of studies related to the automatic mining of assertions for capturing the functionality of behavioural models, where logic expressions among more abstracted (e.g., numeric) variables than bits and bit vectors are necessary.This paper is intended to fill in the gap, by proposing a tool for automatic extraction of temporal assertions from execution traces of behavioural models by adopting a mix of static and dynamic techniques

RTL assertion mining with automated RTLto-TLM abstraction

We present a three-step flow to improve Assertionbased Verification methodology with integrated RTL-to-TLM abstraction: First, an automatic assertion miner generates a large set of possible assertions from an RTL design. Second, automatic assertion qualification identifies the most interesting assertions from this set. Third, the assertions are abstracted to the transaction level, such that they can be re-used in TLM verification. We show that the proposed flow automatically chooses the best assertions among the ones generated to verify the design components when abstracted from RTL to TLM. Our experimental results indicate that the proposed methodology allows us to re-use the most interesting set at TLM without relying on any time consuming or error-prone manual transformations with a considerable amount of speed up and considerable reduction in the execution tim

Design Understanding: From Logic to Specification

We present an outline of the field of Design Understanding and summarize state-of-the-art research in deriving human-understandable knowledge in form of logic properties from an unknown design